Computer-Aided Design Techniques for Low Power Sequential Logic Circuits

Nonfiction, Science & Nature, Technology, Electronics, Circuits, Electricity
Cover of the book Computer-Aided Design Techniques for Low Power Sequential Logic Circuits by Srinivas Devadas, José Monteiro, Springer US
View on Amazon View on AbeBooks View on Kobo View on B.Depository View on eBay View on Walmart
Author: Srinivas Devadas, José Monteiro ISBN: 9781461563198
Publisher: Springer US Publication: December 6, 2012
Imprint: Springer Language: English
Author: Srinivas Devadas, José Monteiro
ISBN: 9781461563198
Publisher: Springer US
Publication: December 6, 2012
Imprint: Springer
Language: English

Rapid increases in chip complexity, increasingly faster clocks, and the proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption of a digital system determines its heat dissipation as well as battery life. For some systems, power has become the most critical design constraint.
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits presents a methodology for low power design. The authors first present a survey of techniques for estimating the average power dissipation of a logic circuit. At the logic level, power dissipation is directly related to average switching activity. A symbolic simulation method that accurately computes the average switching activity in logic circuits is then described. This method is extended to handle sequential logic circuits by modeling correlation in time and by calculating the probabilities of present state lines.
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits then presents a survey of methods to optimize logic circuits for low power dissipation which target reduced switching activity. A method to retime a sequential logic circuit where registers are repositioned such that the overall glitching in the circuit is minimized is also described. The authors then detail a powerful optimization method that is based on selectively precomputing the output logic values of a circuit one clock cycle before they are required, and using the precomputed value to reduce internal switching activity in the succeeding clock cycle.
Presented next is a survey of methods that reduce switching activity in circuits described at the register-transfer and behavioral levels. Also described is a scheduling algorithm that reduces power dissipation by maximising the inactivity period of the modules in a given circuit.
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits concludes with a summary and directions for future research.

View on Amazon View on AbeBooks View on Kobo View on B.Depository View on eBay View on Walmart

Rapid increases in chip complexity, increasingly faster clocks, and the proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption of a digital system determines its heat dissipation as well as battery life. For some systems, power has become the most critical design constraint.
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits presents a methodology for low power design. The authors first present a survey of techniques for estimating the average power dissipation of a logic circuit. At the logic level, power dissipation is directly related to average switching activity. A symbolic simulation method that accurately computes the average switching activity in logic circuits is then described. This method is extended to handle sequential logic circuits by modeling correlation in time and by calculating the probabilities of present state lines.
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits then presents a survey of methods to optimize logic circuits for low power dissipation which target reduced switching activity. A method to retime a sequential logic circuit where registers are repositioned such that the overall glitching in the circuit is minimized is also described. The authors then detail a powerful optimization method that is based on selectively precomputing the output logic values of a circuit one clock cycle before they are required, and using the precomputed value to reduce internal switching activity in the succeeding clock cycle.
Presented next is a survey of methods that reduce switching activity in circuits described at the register-transfer and behavioral levels. Also described is a scheduling algorithm that reduces power dissipation by maximising the inactivity period of the modules in a given circuit.
Computer-Aided Design Techniques for Low Power Sequential Logic Circuits concludes with a summary and directions for future research.

More books from Springer US

Cover of the book Adolescent Substance Abuse by Srinivas Devadas, José Monteiro
Cover of the book Wilson’s Disease by Srinivas Devadas, José Monteiro
Cover of the book Magnetic Resonance in Experimental and Clinical Oncology by Srinivas Devadas, José Monteiro
Cover of the book The Cerebrospinal Fluid by Srinivas Devadas, José Monteiro
Cover of the book High-Risk Sexual Behavior by Srinivas Devadas, José Monteiro
Cover of the book Catalytic Synthesis of Alkene-Carbon Monoxide Copolymers and Cooligomers by Srinivas Devadas, José Monteiro
Cover of the book Clinical Applied Psychophysiology by Srinivas Devadas, José Monteiro
Cover of the book Nuclear Medicine in Tropical and Infectious Diseases by Srinivas Devadas, José Monteiro
Cover of the book From Collective Beings to Quasi-Systems by Srinivas Devadas, José Monteiro
Cover of the book Basics of Software Engineering Experimentation by Srinivas Devadas, José Monteiro
Cover of the book Infectious Disease Informatics by Srinivas Devadas, José Monteiro
Cover of the book The Brain and Regulation of Eye Movement by Srinivas Devadas, José Monteiro
Cover of the book The Mass Psychology of Ethnonationalism by Srinivas Devadas, José Monteiro
Cover of the book Insulin-like Growth Factors and Cancer by Srinivas Devadas, José Monteiro
Cover of the book Biennial Review of Infertility by Srinivas Devadas, José Monteiro
We use our own "cookies" and third party cookies to improve services and to see statistical information. By using this website, you agree to our Privacy Policy